Logic Design and Verification Using SystemVerilog (Revised)

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

Verilog by Example: A Concise Introduction for FPGA Design

Digital Design and Computer Architecture

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Digital Logic RTL & Verilog Interview Questions

Cracking Digital VLSI Verification Interview: Interview Success

SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling

FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC Edition

ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies