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SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
R 2,306
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SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
Country
USA
Brand
Springer
Manufacturer
Springer
Binding
Paperback
ItemPartNumber
16 black & white tables, biography
ReleaseDate
2014-04-13
UnitCount
1
EANs
9781489995001