A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition

The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

Getting Started with UVM: A Beginner's Guide

Digital Logic RTL & Verilog Interview Questions

Practical UVM

Advanced Chip Design, Practical Examples in Verilog

Advanced UVM

Logic Design and Verification Using SystemVerilog (Revised)

Formal Verification: An Essential Toolkit for Modern VLSI Design